Prior top speed of up to 24.2 ns was also achieved by reference design with AMD accelerators
FinTech card designed specifically for fast trade execution and powered by an AMD Virtex UltraScale+ FPGA
It is intended to speed up proprietary trading algorithms in hardware
The best published results to date are achieved by this year’s STAC-T0, which combines the new ultra-low latency TCP-UDP IP stack with Exegy’s FPGA programming framework.
The Virtex UltraScale+ FPGA, designed specifically for electronic trading, powers the Alveo UL3524
The AMD Alveo UL3524 accelerator card is designed to accelerate proprietary trading algorithms in hardware
It has 64 ultra-low latency transceivers, 780K LUTs of FPGA fabric, and 1,680 DSP slices of computing