Altera's new technique uses MLP and LSTM neural networks to recognize and forecast clock drift tendencies in real time to provide AI-driven timing holdover
The direct deployment of these models onto Agilex 7 SoC FPGAs guarantees ultra-low-latency adaptation in the event of GNSS signal loss
Intel solution was created with MATLAB and implemented using Altera’s FPGA AI Suite, Quartus Prime software, and PTP Servo IP
FPGAi allows system architects to include intelligence into hardware that can adapt on its own as networks get closer to the edge and timing issues become more complex
The Agilex 7 outperforms other 7 nm FPGAs in fabric performance per watt. Also offered are 32GB HBM2e, PCIe 5.0, CXL, integrated Arm-based CPUs, and 116Gbps transceivers
General-purpose FPGAs based on Intel’s 10 nm SuperFin manufacturing technology are known as F-Series devices
I-series devices, based on Intel's 10 nm SuperFin process technology, allow PCIe 5.0, cache- and memory-coherent connection to CPUs via Compute Express Link (CXL), and transfer rates up to 116 Gbps
Modern FPGA system-level design uses sophisticated silicon and chiplet technologies for scalability, flexibility, power economy, and hardened function performance