Navigating the Future: PCIe Gen6 and Data Transfer

IP provider Synopsys has been selling its PCIe 6.0 IP package, which includes a controller and physical interface (PHY), since 2021

[{"selector":"#anim-8a778df8-80ae-4029-a068-dfb80f98ba3f [data-leaf-element=\"true\"]","keyframes":{"transform":["translate(0%, 0%) scale(1.5)","translate(0%, 0%) scale(1)"]},"delay":0,"duration":2000,"easing":"cubic-bezier(.3,0,.55,1)","fill":"forwards"}] [{"selector":"#anim-0dfaf335-5bde-4b3e-9de2-d37a5e1491a9","keyframes":[{"offset":0,"transform":"translate3d(0, -145.82748%, 0)","easing":"cubic-bezier(.5, 0, 1, 1)"},{"offset":0.29,"transform":"translate3d(0, 0%, 0)","easing":"cubic-bezier(0, 0, .5, 1)"},{"offset":0.45,"transform":"translate3d(0, -41.006687376%, 0)","easing":"cubic-bezier(.5, 0, 1, 1)"},{"offset":0.61,"transform":"translate3d(0, 0%, 0)","easing":"cubic-bezier(0, 0, .5, 1)"},{"offset":0.71,"transform":"translate3d(0, -13.941107088%, 0)","easing":"cubic-bezier(.5, 0, 1, 1)"},{"offset":0.8,"transform":"translate3d(0, 0%, 0)","easing":"cubic-bezier(0, 0, .5, 1)"},{"offset":0.85,"transform":"translate3d(0, -5.235206532%, 0)","easing":"cubic-bezier(.5, 0, 1, 1)"},{"offset":0.92,"transform":"translate3d(0, 0%, 0)","easing":"cubic-bezier(0, 0, .5, 1)"},{"offset":0.96,"transform":"translate3d(0, -2.274908688%, 0)","easing":"cubic-bezier(.5, 0, 1, 1)"},{"offset":1,"transform":"translate3d(0, 0%, 0)","easing":"cubic-bezier(0, 0, .5, 1)"}],"delay":0,"duration":600,"fill":"both"}]

The silicon implementation of a PCIe 6.0 64 GT/s interface by Alphawave supports the industry’s first CXL 2.0 protocol in addition to operating at full speed with pulse amplitude modulation with four levels (PAM4) signaling with Keysight’s Protocol Exerciser

[{"selector":"#anim-79f18914-baea-4c0f-a4d3-7bdb4a83278c [data-leaf-element=\"true\"]","keyframes":{"transform":["translate3d(-7.735655481246508%, 0, 0)","translate3d(0%, 0, 0)"]},"delay":0,"duration":2000,"easing":"cubic-bezier(.3,0,.55,1)","fill":"both"}] [{"selector":"#anim-8a3623c8-775f-44b6-9363-4bb36dff87ba","keyframes":{"opacity":[0,1]},"delay":0,"duration":600,"easing":"cubic-bezier(0.4, 0.4, 0.0, 1)","fill":"both"}]

Implementation fully supports FLIT mode, PCIe Gen6’s Forward Error Correction (FEC), and other new interconnection standard feature

[{"selector":"#anim-ec9cdfcc-5261-47d0-a01c-5d353949e4ad [data-leaf-element=\"true\"]","keyframes":{"transform":["translate3d(34.249999904429615%, 0, 0)","translate3d(0%, 0, 0)"]},"delay":0,"duration":2000,"easing":"cubic-bezier(.3,0,.55,1)","fill":"both"}] [{"selector":"#anim-756ce655-e68d-481d-8eff-c02e52a6ca7e","keyframes":{"transform":["rotate(-540deg) scale(0.1)","none"],"opacity":[0,1]},"delay":0,"duration":1000,"fill":"both","iterations":1}]

Pulse Amplitude Modulation (PAM4) with four levels of signaling, leveraging PAM4 that is currently in use in the market

[{"selector":"#anim-8875ec59-941d-436f-adcc-0af4fe18f0de [data-leaf-element=\"true\"]","keyframes":{"transform":["translate3d(-34.249999904429615%, 0, 0) translate(-25%, 0%) scale(1.5)","translate3d(0%, 0, 0) translate(0%, 0%) scale(1)"]},"delay":0,"duration":2000,"fill":"forwards"}] [{"selector":"#anim-b39917cf-fd13-4940-8c78-8148c0c7a915","keyframes":{"transform":["translate3d(146.28822%, 0px, 0)","translate3d(0px, 0px, 0)"]},"delay":0,"duration":600,"easing":"cubic-bezier(0.4, 0.4, 0.0, 1)","fill":"both"}] [{"selector":"#anim-bcb12172-40f8-4323-bedf-2810c7f49377","keyframes":{"opacity":[0,1]},"delay":0,"duration":600,"easing":"cubic-bezier(0.4, 0.4, 0.0, 1)","fill":"both"}] [{"selector":"#anim-2a6902b8-8ff1-42d5-8bc2-6f0e9f492a0c","keyframes":{"transform":["scale(0.15)","scale(1)"]},"delay":0,"duration":600,"easing":"cubic-bezier(0.4, 0.4, 0.0, 1)","fill":"forwards"}]

Cyclic Redundancy Check (CRC) and Lightweight Forward Error Correct (FEC) reduce the bit error rate increase linked to PAM4 signaling

[{"selector":"#anim-971ea475-e889-4b84-9c07-e9ec426715e7 [data-leaf-element=\"true\"]","keyframes":{"transform":["translate3d(34.59158406491817%, 0, 0)","translate3d(0%, 0, 0)"]},"delay":0,"duration":2000,"easing":"cubic-bezier(.3,0,.55,1)","fill":"both"}] [{"selector":"#anim-ef0fbb4c-95b6-4a29-b431-6995552e5405","keyframes":{"transform":["translate3d(-123.57143%, 0px, 0)","translate3d(0px, 0px, 0)"]},"delay":0,"duration":1000,"easing":"cubic-bezier(.2, 0, .8, 1)","fill":"both"}] [{"selector":"#anim-d78d4ad1-a1d3-4210-8de3-80436a4af316","keyframes":{"transform":["rotateZ(-180deg)","rotateZ(0deg)"]},"delay":0,"duration":1000,"easing":"cubic-bezier(.2, 0, .5, 1)","fill":"forwards"}]

Double the bandwidth gain is possible with Flit (flow control unit) based encoding, which also supports PAM4 modulation and cooperates with the FEC and CRC

[{"selector":"#anim-baaa6f5f-d940-46af-8f68-07df0674bcc3 [data-leaf-element=\"true\"]","keyframes":{"transform":["translate3d(-32.75261313576164%, 0, 0) translate(-25%, 0%) scale(1.5)","translate3d(0%, 0, 0) translate(0%, 0%) scale(1)"]},"delay":0,"duration":2000,"fill":"forwards"}] [{"selector":"#anim-c5542d1f-77d3-4df7-8ef8-54fd3a3fd411","keyframes":{"transform":["translate3d(-121.52777%, 0px, 0)","translate3d(0px, 0px, 0)"]},"delay":0,"duration":600,"easing":"cubic-bezier(0.4, 0.4, 0.0, 1)","fill":"both"}] [{"selector":"#anim-3c581d8a-0827-4a7c-a4d6-e42f7879fcb2","keyframes":{"opacity":[0,1]},"delay":0,"duration":600,"easing":"cubic-bezier(0.4, 0.4, 0.0, 1)","fill":"both"}] [{"selector":"#anim-99630a1e-8c64-4d38-9c30-ea5311e86b8f","keyframes":{"transform":["scale(0.15)","scale(1)"]},"delay":0,"duration":600,"easing":"cubic-bezier(0.4, 0.4, 0.0, 1)","fill":"forwards"}]

Moreover, the CXL 3.0 protocol allows for additional expansion of this PCIe Gen6 platform For More Details Govindhtech.com

[{"selector":"#anim-e96e219c-85b1-45b6-9f60-4af3408d6cb7 [data-leaf-element=\"true\"]","keyframes":{"transform":["translate3d(-34.249999904429615%, 0, 0)","translate3d(0%, 0, 0)"]},"delay":0,"duration":2000,"easing":"cubic-bezier(.3,0,.55,1)","fill":"both"}]