Navigating the Future: PCIe Gen6 and Data Transfer

IP provider Synopsys has been selling its PCIe 6.0 IP package, which includes a controller and physical interface (PHY), since 2021

The silicon implementation of a PCIe 6.0 64 GT/s interface by Alphawave supports the industry’s first CXL 2.0 protocol in addition to operating at full speed with pulse amplitude modulation with four levels (PAM4) signaling with Keysight’s Protocol Exerciser

Implementation fully supports FLIT mode, PCIe Gen6’s Forward Error Correction (FEC), and other new interconnection standard feature

Pulse Amplitude Modulation (PAM4) with four levels of signaling, leveraging PAM4 that is currently in use in the market

Cyclic Redundancy Check (CRC) and Lightweight Forward Error Correct (FEC) reduce the bit error rate increase linked to PAM4 signaling

Double the bandwidth gain is possible with Flit (flow control unit) based encoding, which also supports PAM4 modulation and cooperates with the FEC and CRC